1. Field of the Invention
The present invention relates to a memory access controlling system for allowing a processor to interleave-access a main memory (composed of memory devices such as a RAM (Random Access Memory) and a DRAM (Dynamic RAM)).
2. Description of the Prior Art
In a recent computer system, a controlling process for allowing the memory access speed to be raised to that close to the processor speed is used. This controlling process is referred to as an interleaving process. In the interleaving process, the main memory is divided into a plurality of areas referred to as banks. In the individual banks, data are accessed (read and written) simultaneously or alternately. Thus, the process speed of the computer system can be prevented from being lowered even when the main memory is accessed.
However, recent computer systems are being downsized and becoming open-structured. In other words, functions different from conventional mainframe functions are being desired. As an example, a function for allowing memory devices having different storage capacities to be simultaneously used as the main memory is known.
In a conventional memory access controlling system, when a main memory composed of a plurality of memory devices having different storage capacities is interleaved, the memory devices are interleaved corresponding to the smallest storage capacity of a memory device therein.
As described above, in the conventional memory access controlling system, when a main memory composed of a plurality of memory devices having different storage capacities is interleaved, since the memory devices are interleaved corresponding to the smallest storage capacity of a memory device therein, the storage capacities of the memory devices having larger storage capacities than the smallest storage capacity are not effectively used.
Since the integration of memory devices is drastically improving, when the user wants to extend the main memory, an additional memory device having a storage capacity twice or four times larger than that of a memory device already used in the main memory may be used. In this case, the above-described disadvantage will frequently occur. In order to solve such a disadvantage, if memory devices used in the main memory are substituted with memory devices having larger storage capacities than those, the original memory devices will be removed and become wasteful.
As a related art reference for dealing with a change of storage capacities for the interleave-controlling process, a technology has been disclosed as, for example, JPA 6-309223 titled xe2x80x9cStoring Apparatus Having Memory Interleaving Functionxe2x80x9d.
In the related art reference, each bank is divided into blocks with the same size. The memory implementation states of individual blocks are stored to a configuration register. When the processor designates an address to be accessed, with reference to the configuration register, the address is converted corresponding to the memory implementation state. Thus, even if the main memory is extended by one bank, the main memory can be interleaved.
However, according to such a related art reference, since only the storage capacity of each of a plurality of DRAMs and bank number information thereof are stored, if the DRAMs have different storage capacities, it is difficult to interleave the main memory.
In order to overcome the aforementioned disadvantage, the present invention has been made and accordingly, have a purpose to provide a memory access controlling system which allows a main memory composed of a plurality of memory devices having different storage capacities to be equally interleaved and the storage capacities of the memory devices to be effectively used.
According to the present invention, there is provided a memory access controlling system for hierarchically interleaving a memory in a unit of memory module and accessing the memory, comprising: a bank control table having entries corresponding to units, each of the entries containing data for a plurality of the memory modules, the data for each of the memory modules having a presence bit and a source address to be converted to a row address the memory module concerned, the presence bit representing whether or not a memory device is mounted on the memory module concerned; an address bit position table containing information which represents both the number of bits of the row address and the number of bits of the column address of a memory device, if any, mounted on each of the memory modules; a decoder for obtaining the number of the unit to be accessed on the basis of a line address which is supplied from an access source; a number determining portion for determining the memory module to be accessed on the basis of the line address and the presence bit in the data contained in an entry of the bank control table having the number obtained by the decoder; and an address determining portion for searching the address bit position table for information that represents both the number of bits of the row address and the number of bits of the column address of the memory device mounted on the memory module determined by the number determining portion, and in addition determining both the row address and the column address of the memory module to be accessed on the basis of the line address, a source address to be converted to the row address of the memory module to be accessed, the source address being included in data contained in the entry having the number obtained by the decoder, and the searched information representing both the number of bits of the row address and the number of bits of the column address.
The memory access controlling system may further comprises: a buffer group for storing a plurality of implementation addresses, each of which is composed of the number of the memory module determined by the number determining portion and the row address and column address determined by the address determining portion; and an arbitrator for arbitrating the plurality of implementation addresses stored in the buffer group.
In the memory access controlling system, an equal storage capacity may be allocated to each of the units.
In the memory access controlling system, the storage capacity of each of the units may be the same as the storage capacity of a memory module having the smallest storage capacity.
In the memory access controlling system, the hierarchy of the memory modules may have a two-branch tree structure.
In the memory access controlling system, an equal storage capacity may be allocated to gatherings in the same hierarchical level for each of the unit.
These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of the best mode of embodiment thereof, as illustrated in the accompanying drawings.